The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 20, 2009
Filed:
Sep. 12, 2006
Kevin W. Gorman, Fairfax, VT (US);
Emory D. Keller, Milton, VT (US);
Michael R. Ouellette, Westford, VT (US);
Donald L. Wheater, Hinesburg, VT (US);
Kevin W. Gorman, Fairfax, VT (US);
Emory D. Keller, Milton, VT (US);
Michael R. Ouellette, Westford, VT (US);
Donald L. Wheater, Hinesburg, VT (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A system and method for performing high speed memory diagnostics via built-in-self-test (BIST). A test system includes a tester for testing an integrated circuit that includes a BIST circuit and a test control circuit. The BIST circuit further includes a BIST engine and fail logic for testing an imbedded memory array. The test control circuit includes three binary up/down counters, a variable delay, and a comparator circuit. A method includes presetting the counters of the test control circuit, presetting the variable delay to a value that is equal to the latency of the fail logic, setting the BIST cycle counter to decrement mode, presetting the variable delay to zero, re-executing the test algorithm, performing a second test operation of capturing the fail data, and performing a third test operation of transmitting the fail data to the tester.