The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 20, 2009
Filed:
Mar. 24, 2006
Applicants:
Jorge Ernesto Carrillo, San Jose, CA (US);
Satish R. Ganesan, Mountain View, CA (US);
Amit Kasat, Cupertino, CA (US);
Sivakumar Velusamy, San Jose, CA (US);
Inventors:
Jorge Ernesto Carrillo, San Jose, CA (US);
Satish R. Ganesan, Mountain View, CA (US);
Amit Kasat, Cupertino, CA (US);
Sivakumar Velusamy, San Jose, CA (US);
Assignee:
Xilinx, Inc., San Jose, CA (US);
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract
A system for performing cycle accurate simulation of a circuit design can include a plurality of cycle accurate models, wherein each cycle accurate model is a software object representation of a hardware function, and a scheduler configured to execute each cycle accurate model at clock cycle boundaries determined during a simulation session.