Circuit for bit alignment in high speed multichannel data transmission

Abstract

An alignment circuit is configured to receive a reference clock signal (ref_clk) derived from a main clock having a period T and successive sets of 2n data bits that are transmitted in parallel on a data bus wherein said data bits are aligned with respect to said reference clock signal but misaligned with respect to each other. It first comprises a plurality of n aligners. Each aligner is coupled to said reference clock and a pair of said data bits, referred to as primary bits, one data bit (bit_tdat(i)) having the rank (i) in a determined set and the other being the corresponding data bit (bit_tdat(i+n)) having the rank (i+n) in the set. Each aligner comprises first, second and third shifting means for shifting said primary data bits to respectively generate respective data bits delayed of one, two and two and half cycles and a multiplexor receiving said primary and delayed data bits under the control of three control signals of a first type (recal(i), realign(i) and realign(i)) to generate a pair of aligned data bits (tdat_desk(i) & tdat_desk(i+n)).