The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 20, 2009
Filed:
Oct. 04, 2004
Sang-guk Han, Hwaseong-si, KR;
Chan-min Han, Hwaseong-si, KR;
Sang-Guk Han, Hwaseong-si, KR;
Chan-Min Han, Hwaseong-si, KR;
Samsung Electronics Co., Ltd., Gyeonggi-do, KR;
Abstract
A semiconductor device including a PCB including conductive patterns formed on at least one surface of the PCB, external connection terminals including at least one ground terminal and coupled to the conductive patterns, at least one semiconductor chip mounted on a surface of the PCB, and an ESD protection pattern being coupled to at least one of the least one ground terminal, the at least one ground terminal not being coupled to the conductive patterns. A semiconductor memory device, including a PCB, a memory chip mounted on a first surface of the PCB, external connection terminals formed on a second surface of the PCB, and a first ESD protection pattern being coupled to at least one ground terminal. A method of mitigating ESD in a semiconductor device, including mounting a chip on a PCB, forming conductive patterns on the PCB, and forming at least one ESD protection pattern on the PCB, the ESD protection pattern being connected to a ground terminal and not being coupled to the conductive patterns.