The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 20, 2009
Filed:
Jun. 25, 2004
Won-ho Cho, Gyeongsangbuk-do, KR;
Gyoo-chul JO, Gunpo-si, KR;
Gue-tai Lee, Gyeongsangbuk-do, KR;
Jin-gyu Kang, Icheon, KR;
Beung-hwa Jeong, Gyeongsangbuk-do, KR;
Jin-young Kim, Incheon, KR;
Won-Ho Cho, Gyeongsangbuk-do, KR;
Gyoo-Chul Jo, Gunpo-si, KR;
Gue-Tai Lee, Gyeongsangbuk-do, KR;
Jin-Gyu Kang, Icheon, KR;
Beung-Hwa Jeong, Gyeongsangbuk-do, KR;
Jin-Young Kim, Incheon, KR;
LG Display Co., Ltd., Seoul, KR;
Abstract
The present invention is an array substrate for use in a liquid crystal display device, which includes a gate electrode, a gate line and a gate pad on a substrate, wherein the gate electrode, the gate line and the gate pad have a double-layered structure consisting of a first metal layer and a first barrier metal layer in series from the substrate, and wherein the first metal is one of aluminum and aluminum alloy; a gate insulation layer on the substrate covering the gate electrode, gate line and gate pad; an active layer and an ohmic contact layer sequentially formed on the gate insulation layer and over the gate electrode; a data line on the gate insulation layer perpendicularly crossing the gate line, source and drain electrodes contacting the ohmic contact layer, and a data pad on the gate insulation layer, wherein the data line, the source and drain electrode and the data pad have a double-layered structure consisting of a second barrier metal layer and a second metal layer of copper; a passivation layer formed on the gate insulation layer to cover the data line, source and drain electrodes, and data pad, wherein the passivation layer has a drain contact hole exposing a portion of the drain electrode, a gate pad contact hole exposing a portion of the gate pad, and a data pad contact hole exposing a portion of the data pad; and a pixel electrode, a gate pad terminal and a data pad terminal on the passivation layer, all of which are formed of a transparent conductive material on the passivation layer.