The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 20, 2009

Filed:

Sep. 06, 2005
Applicant:

Akira Yukawa, Kanagawa, JP;

Inventor:

Akira Yukawa, Kanagawa, JP;

Assignee:

NEC Electronics Corporation, Kawasaki, Kanagawa, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01); G01R 19/00 (2006.01); H03F 3/45 (2006.01);
U.S. Cl.
CPC ...
Abstract

There is provided a voltage comparator circuit with even lower power consumption. It comprises an FET Q, to the gate of which a signal input terminal INis connected, an FET Q, to the gate of which a signal input terminal INis connected, a bistable circuit, an AND circuit G, and an FET Q. A pulse signal φ, which becomes a strobe signal for the comparison, is supplied to the bistable circuit, and when the pulse signal φ is at a low level, the logic values of output terminals OUTand OUTgo to a high level, and the output of the AND circuit G becomes high, turning the FET Qon. When the pulse signal φ changes to a high level from a low level, input voltages are compared, one of the output terminals OUTor OUTchanges to a low level, corresponding to the value relationship between the drain currents of the FETs Qand Q, and the output of the AND circuit G goes to a low level, turning the FET Qoff. The power consumption is reduced because the source currents of the FETs Qand Qflow only during a short period of time when the operation of comparison is being performed.


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