The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 20, 2009

Filed:

May. 22, 2006
Applicants:

Isik C. Kizilyalli, Millburn, NJ (US);

Joseph Rudolph Radosevich, Orlando, FL (US);

Pradip Kumar Roy, Orlando, FL (US);

Inventors:

Isik C. Kizilyalli, Millburn, NJ (US);

Joseph Rudolph Radosevich, Orlando, FL (US);

Pradip Kumar Roy, Orlando, FL (US);

Assignee:

Agere Systems Inc., Allentown, PA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/22 (2006.01); H01L 21/38 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of manufacture for semiconductor electronic products and a circuit structure. A semiconductor material has a surface region and dopant is provided to a portion of the surface region. The portion of the surface region provided with the dopant is irradiated with sufficient energy to induce diffusion of the dopant from the portion of the surface region to another region of the semiconductor material. A method for manufacturing an electronic product with a semiconductor material having a surface and two spaced-apart regions along the surface for receiving dopant includes forming a field effect transistor gate structure is along the surface and over a third region of the surface between the two spaced-apart regions. Dopant is provided to the spaced-apart regions which are heated to a temperature at least 50 degrees C. higher than the peak temperature which results in the third region when the spaced-apart regions are heated. A circuit comprises a semiconductor material having a surface region for formation of devices, a field effect transistor gate structure formed on the surface region, the gate structure including a conductive layer and an amorphous insulative layer having a dielectric constant greater than five relative to free space. The insulative layer is formed between the conductive layer and the surface region. A source region is formed along the surface region and a drain region is also formed along the surface region. The gate structure, source region and drain region are configured to form an operable field effect transistor.


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