The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 13, 2009
Filed:
Nov. 27, 2006
Yeong-jar Chang, Taichung County, TW;
Yeong-Jar Chang, Taichung County, TW;
Faraday Technology Corp., Science-Based Industrial Park, Hsin-Chu, TW;
Abstract
A BIST circuit for testing both an analog-to-digital converter and a phase lock loop includes a controllable delay circuit, a NAND gate, a dividing circuit, a NOR gate and a charge/discharge circuit. The invention reduces the period of the signal under test, converts its pulse width to voltage and measures the output via an ADC. The clock jitter becomes sensitive through a delay cancellation method, thus, the accuracy is improved. The invention further comprises all testing procedure for period jitters of a PLL and static characteristics of an ADC. The test error caused by process variation can be corrected by a controllable delay circuit such that the error determination of the test result is prevented.