The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 13, 2009

Filed:

Jan. 25, 2007
Applicants:

Kousuke Komikado, Odawara, JP;

Koji Iwamitsu, Odawara, JP;

Tetsuya Shirogane, Odawara, JP;

Atsushi Ishikawa, Minamiashigara, JP;

Takahide Okuno, Odawara, JP;

Mitsuhide Sato, Oiso, JP;

Toshiaki Minami, Odawara, JP;

Hiroaki Yuasa, Ninomiya, JP;

Inventors:

Kousuke Komikado, Odawara, JP;

Koji Iwamitsu, Odawara, JP;

Tetsuya Shirogane, Odawara, JP;

Atsushi Ishikawa, Minamiashigara, JP;

Takahide Okuno, Odawara, JP;

Mitsuhide Sato, Oiso, JP;

Toshiaki Minami, Odawara, JP;

Hiroaki Yuasa, Ninomiya, JP;

Assignee:

Hitachi, Ltd., Tokyo, JP;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 3/00 (2006.01); G06F 9/46 (2006.01);
U.S. Cl.
CPC ...
Abstract

Provided is a storage subsystem capable of improving the data processing speed by balancing the load on processors and controllers. This storage subsystem includes a controller for controlling the input and output of data to and from a storage apparatus that provides to a host computer a plurality of logical units to become a storage extent for the host computer to read and write data, processes a command issued by the host computer, and has a storage resource in relation to the logical unit. The controller has a local memory for storing the command, and a processor configured from a plurality of cores for controlling the input and output of data to and from the logical unit to be subject to the input and output of the data based on the command. The local memory stores association information representing the correspondence between the plurality of logical units and the plurality of cores. Each of the plurality of cores processes the command to the logical unit to be handled by a self core based on the association information and executes I/O processing of the data to the logical unit.


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