The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 13, 2009
Filed:
Jun. 26, 2006
Hidetoshi Sugiyama, Kawasaki, JP;
Masao Nakajima, Kawasaki, JP;
Haruyuki Mouri, Kawasaki, JP;
Hideaki Suzuki, Kawasaki, JP;
Hidetoshi Sugiyama, Kawasaki, JP;
Masao Nakajima, Kawasaki, JP;
Haruyuki Mouri, Kawasaki, JP;
Hideaki Suzuki, Kawasaki, JP;
Fujitsu Microelectronics Limited, Tokyo, JP;
Abstract
A testing circuit for a semiconductor device having a test mode in which the information about built-in memory cannot be read after conducting a test on a semiconductor device, and cutting a pad formed in a scribe area is provided. The scribe PAD and the scribe ROM are formed in the cutting area of a wafer. Upon power-up of a chip a, the power-on reset circuit transmits a reset signal to the mode register. After setting the initial resister value to '00', a mode switch signal is input from the mode switch terminal, the scribe ROM is activated, and the test mode is set. In this process, a Manchester coded signal is provided from the scribe PAD, decoded by a clock of dividing frequency provided from the clock dividing circuit, the value of the register in the test mode in the mode register is set, and external reset is asserted or negated.