The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 13, 2009
Filed:
Mar. 27, 2008
Paul Wilson, Linlithgow, GB;
Roel Van Ettinger, Bathgate, GB;
Paul Wilson, Linlithgow, GB;
Roel van Ettinger, Bathgate, GB;
Micrel, Incorporated, San Jose, CA (US);
Abstract
Evaluating an embedded EPROM in a host IC device involves using program circuitry to program/unprogram all of the floating-gate cells of the embedded EPROM, then simultaneously transmitting a predetermined test bias voltage to all of the programmed/unprogrammed floating-gate cells, and then evaluating the output terminals of all of the floating-gate cells using a logic (e.g., wired NOR or NAND) circuit, whereby successful operation of all of the embedded EPROM cells causes the wired logic circuit to generate a single positive test result signal, and the failure of one or more of the embedded EPROM cells causes the wired logic circuit to generate a single negative test signal. A reference cell is also evaluated using a bias testing circuit to determine that the reference voltage supplied during normal operation is at an acceptable voltage level.