The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 13, 2009
Filed:
Sep. 25, 2008
Pavel Poplevine, Foster City, CA (US);
Annie-li-keow Lum, Milpitas, CA (US);
Andrew Cao, Fremont, CA (US);
Ernes Ho, Sunnyvale, CA (US);
Pavel Poplevine, Foster City, CA (US);
Annie-Li-Keow Lum, Milpitas, CA (US);
Andrew Cao, Fremont, CA (US);
Ernes Ho, Sunnyvale, CA (US);
National Semiconductor Corporation, Santa Clara, CA (US);
Abstract
A method of making a non-volatile memory (NVM) cell structure includes the formation of a first NVM cell, a second NVM cell and an SRAM cell that includes first and second data nodes. A first pass gate structure is connected between the first NVM cell and the first data node of the SRAM cell, the first pass gate structure being responsive to first and second states of a first pass gate signal to respectively couple and decouple the first NVM cell and the SRAM cell. A first equalize structure is formed to connect the first pass gate structure and the first NVM cell and is responsive to a first equalize signal to connect the first NVM cell to ground. A second pass gate structure is connected between the second NVM cell and the second data node of the SRAM cell, the second pass gate structure being responsive to first and second states of a second pass gate signal to respectively couple and decouple the second NVM cell and the SRAM cell. A second equalize structure is connected between the second pass gate structure and the second NVM cell, the second equalize structure being responsive to a second equalize signal to connect the second NVM cell to ground. Appropriate biasing conditions are applied to the NVM cell structure to implement program/operations.