Voltage multiplier with improved efficiency

Abstract

A multi-stage voltage multiplication circuit and methodology are provided which use a multi-stage charge pump boosting circuit () and two-stage pass gate circuit () having complementary power switches (M, M, M, M) to efficiently develop an output voltage (V) that is higher than the input supply voltage (V). By using a two-stage complementary switch to connect boosted clock signals (P, P) from a charge pump () to the multiplier output (V), return current from the storage capacitor (C) to the pumping capacitor (C, C) is blocked, thereby increasing power transfer efficiency, even at high clock frequencies. In addition, a boosted auxiliary voltage is generated by an additional boosting stage () and applied to the PMOS wells of the pass gate circuit (), thereby preventing latch-up and backflow.