The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 13, 2009
Filed:
Mar. 26, 2007
Javier A. Salcedo, Orlando, FL (US);
Juin J. Liou, Oviedo, FL (US);
Joseph C. Bernier, Palm Bay, FL (US);
Donald K. Whitney, Jr., W. Melbourne, FL (US);
Javier A. Salcedo, Orlando, FL (US);
Juin J. Liou, Oviedo, FL (US);
Joseph C. Bernier, Palm Bay, FL (US);
Donald K. Whitney, Jr., W. Melbourne, FL (US);
Intersil Americas Inc., Milpitas, CA (US);
University of Central Florida, Orlando, FL (US);
Abstract
A complementary SCR-based structure enables a tunable holding voltage for robust and versatile ESD protection. The structureare n-channel high-holding-voltage low-voltage -trigger silicon controller rectifier (N-HHLVTSCR) device and p-channel high-holding-voltage low-voltage -trigger silicon controller rectifier (P-HHLVTSCR) device. The regions of the N-HHLVTSCR and P-HHLVTSCR devices are formed during normal processing steps in a CMOS or BICMOS process. The spacing and dimensions of the doped regions of N-HHLVTSCR and P-HHLVTSCR devices are used to produce the desired characteristics. The tunable HHLVTSCRs makes possible the use of this protection circuit in a broad range of ESD applications including protecting integrated circuits where the I/O signal swing can be either within the range of the bias of the internal circuit or below/above the range of the bias of the internal circuit.