The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 13, 2009

Filed:

Apr. 19, 2005
Applicants:

Chikage Noritake, Ama-gun, JP;

Yoshitsugu Sakamoto, Toyohashi, JP;

Akira Tanahashi, Okazaki, JP;

Hideki Okada, Aichi-gun, JP;

Tomomasa Yoshida, Aichi-gun, JP;

Inventors:

Chikage Noritake, Ama-gun, JP;

Yoshitsugu Sakamoto, Toyohashi, JP;

Akira Tanahashi, Okazaki, JP;

Hideki Okada, Aichi-gun, JP;

Tomomasa Yoshida, Aichi-gun, JP;

Assignees:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/44 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method for manufacturing a semiconductor device having a solder layer includes the steps of: grinding a mounting surface of a semiconductor chip; etching the mounting surface of the chip; forming an electrode on the mounting surface of the chip; assembling the chip, the solder layer and a base in this order; and heating the chip, the solder layer and the base to be equal to or higher than a solidus temperature of the solder layer so that the solder layer is reflowed for soldering the chip on the base.


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