The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 06, 2009
Filed:
Sep. 28, 2005
Jeffrey M. Mason, Eldorado Springs, CO (US);
Jay T. Young, Louisville, CO (US);
Jeffrey M. Mason, Eldorado Springs, CO (US);
Jay T. Young, Louisville, CO (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
Method, apparatus, and computer readable medium for modular circuit design for a programmable logic device (PLD) is described. In one example, a circuit design is captured. The circuit design includes a plurality of modules and one or more logic interface macros positioned on a floorplan. Each of the plurality of modules is one of a static module or a reconfigurable module. The one or more logic interface macros include programmable logic of the PLD and are positioned at one or more boundaries between one or more pairs of the plurality of modules. Each of the plurality of modules is implemented using information generated from the capturing step. The modules are assembled using the information generated from the capturing step and implementing step. Routing for a static module can cross a defined implementation area for a reconfigurable module, and a static module can be placed anywhere outside of reconfigurable module areas.