The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 06, 2009
Filed:
Aug. 13, 2004
Mark H. Costin, Bloomfield Township, MI (US);
Timothy J. Hartrey, Brighton, MI (US);
Tyrus J. Valascho, Clarkston, MI (US);
Steven P. Sullivan, Ann Arbor, MI (US);
William Robert Mayhew, Ann Arbor, MI (US);
Ananth Krishnan, Ypsilanti, MI (US);
Jinchun Peng, Westland, MI (US);
Mark H. Costin, Bloomfield Township, MI (US);
Timothy J. Hartrey, Brighton, MI (US);
Tyrus J. Valascho, Clarkston, MI (US);
Steven P. Sullivan, Ann Arbor, MI (US);
William Robert Mayhew, Ann Arbor, MI (US);
Ananth Krishnan, Ypsilanti, MI (US);
Jinchun Peng, Westland, MI (US);
GM Global Technology Operations, Inc., Detroit, MI (US);
Abstract
A method of verifying the integrity of an arithmetic logic unit (ALU) of a control module includes inputting a first test value into one of a plurality of registers of the ALU and inputting a second test value into remaining registers of the plurality of registers. A first set of operations is performed between the one of the plurality of registers and each of the remaining registers to produce a first set of results. A fault is indicated when one of the first set of results varies from a first predetermined result.