The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 06, 2009
Filed:
Jan. 09, 2008
Martha Mercaldi-kim, Seattle, WA (US);
Mark Oskin, Seattle, WA (US);
John Davis, San Francisco, CA (US);
Todd Austin, Ann Arbor, MI (US);
Mojtaba Mehrara, Ann Arbor, MI (US);
Martha Mercaldi-Kim, Seattle, WA (US);
Mark Oskin, Seattle, WA (US);
John Davis, San Francisco, CA (US);
Todd Austin, Ann Arbor, MI (US);
Mojtaba Mehrara, Ann Arbor, MI (US);
University of Washington, Seattle, WA (US);
Microsoft Corporation, Redmond, WA (US);
Regents of the U of Michigan, Ann Arbor, MI (US);
Abstract
A fabrication technique called 'component and polymorphic network,' in which semiconductor chips are made from small prefabricated bare electronic component dies, e.g., application specific integrated circuits (ASICs), that are assembled according to designer specifications, and bonded to a semiconductor substrate comprising the polymorphic network. The component and polymorphic network assembly has a low overhead for producing custom chips. In another exemplary embodiment, the polymorphic network can be combined with functional components in a single die. The interconnect scheme for ports on the polymorphic network can be configured or reconfigured with configuration data prior to the runtime of an application, to achieve different interconnect schemes.