The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 29, 2009

Filed:

Jan. 23, 2006
Applicants:

Ting-cheng Hsu, Hsin-Chu, TW;

Yen-yu Lin, Hsin-Chu Hsien, TW;

Chih-wei Ko, Taipei, TW;

Chang-fu Lin, Hsin-Chu, TW;

Inventors:

Ting-Cheng Hsu, Hsin-Chu, TW;

Yen-Yu Lin, Hsin-Chu Hsien, TW;

Chih-Wei Ko, Taipei, TW;

Chang-Fu Lin, Hsin-Chu, TW;

Assignee:

MediaTek Inc., Hsin-Chu Hsien, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 13/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A processing module with multilevel cache architecture, including: a processor; a level-one (L1) cache, coupled to the processor, for caching data for the processor, wherein the L1 cache has at least one L1 cacheable range; a level-two (L2) cache, coupled to the L1 cache, for caching data for the processor, wherein the L2 cache has at least one L2 cacheable range, and the L1 cacheable range and the L2 cacheable range are mutually exclusive; and a memory interface, coupled to the L1 cache and the L2 cache, for transferring data between the L1 cache and a memory and for transferring data between the L2 cache and the memory.


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