The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7596482 B1

PDF
Full Text
Expired
Date of Patent:
Sep. 29, 2009

Filed:

May. 25, 2006
Applicants:

Rajen J. Murugan, Round Rock, TX (US);

Sarat Kirshnan, Round Rock, TX (US);

Inventors:

Rajen J. Murugan, Round Rock, TX (US);

Sarat Kirshnan, Round Rock, TX (US);

Assignee:

Dell Products L.P., Round Rock, TX (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); G06F 7/60 (2006.01); G06F 17/10 (2006.01);
U.S. Cl.
CPC ...
Abstract

Determining ampacity risks in a circuit comprises receiving geometry data of the circuit, initializing boundary conditions, initializing circuit geometry assumptions, modeling the circuit geometry data as a three-dimensional solid, computing non-Fourier heat conduction through the three-dimensional solid model using conjugate gradient numerical analysis with an incomplete Cholesky preconditioner, and generating an output indicative of a location in the three-dimensional solid model where potential thermal damage may occur in response to a predetermined excitation.


Find Patent Forward Citations

Murugan, Rajen. (2009). System and method to analyze and determine ampacity risks on pcb interconnections (U.S. Patent No. 7596482). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7596482

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