Floating body control in soi dram

Abstract

A system including a DRAM memory device on an integrated circuit (IC) using a control logic device to initiate a body refresh operation to provide a means for maintaining a low voltage at a floating body and discourage data loss, and a design structure including the DRAM memory device embodied in a machine readable medium is provided. A plurality of DRAM cells are connected to a first word line circuit and a first bit line circuit. The control logic device is coupled to the DRAM memory device and the IC for initiating the body refresh cycle. The control logic communicates with a first bit line and word line circuits and communicates with a reference word line and bit line circuits. A sense amplifier circuit and signal is provided for amplifying the voltage at the first bit line and the reference bit line. The body refresh cycle includes deactivating the first word line voltage while the first bit line and reference bit line voltages continue.