The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 29, 2009

Filed:

Jun. 28, 2006
Applicants:

Akira Ogawa, Tokyo, JP;

Masaru Yano, Tokyo, JP;

Inventors:

Akira Ogawa, Tokyo, JP;

Masaru Yano, Tokyo, JP;

Assignee:

Sapnsion LLC, Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 16/06 (2006.01);
U.S. Cl.
CPC ...
Abstract

The present invention provides a semiconductor memory and a control method therefor, the semiconductor device including a first current-voltage conversion circuit () connected to a core cell () provided in a nonvolatile memory cell array (), a second current-voltage conversion circuit () connected to a reference cell () through a reference cell data line (), a sense amplifier () sensing an output from the first current-voltage conversion circuit and an output from the second current-voltage conversion circuit, a compare circuit () comparing a voltage level at the reference cell data line with a predefined voltage level, and a charging circuit () charging the reference cell data line, if the voltage level at the reference cell data line is lower than the predefined voltage level during pre-charging the reference cell data line. According to the present invention, the pre-charging period of the reference cell data line can be shortened, and the data read time can be shortened.


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