The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 29, 2009
Filed:
Mar. 23, 2007
Chih-ming Hung, McKinney, TX (US);
Charvaka Duvvury, Plano, TX (US);
Chih-Ming Hung, McKinney, TX (US);
Charvaka Duvvury, Plano, TX (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
An ESD protection circuit is designed on an integrated circuit () having a first power supply bus () and a second power supply bus (). The circuit includes a first logic gate () having a current path coupled to the first power supply bus. The first logic gate includes an output terminal. A second logic gate () has a current path coupled to the second power supply bus. The second logic gate has an input terminal coupled to the output terminal of the first logic gate. A first device () is coupled in series with the current path of the second logic gate and is always on during normal circuit operation.