The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 29, 2009
Filed:
Apr. 25, 2006
Joseph A. Cetin, San Diego, CA (US);
Jason F. Muriby, San Diego, CA (US);
Matthew D. Sienko, La Jolla, CA (US);
Joseph A. Cetin, San Diego, CA (US);
Jason F. Muriby, San Diego, CA (US);
Matthew D. Sienko, La Jolla, CA (US);
Cypress Semiconductor Corporation, San Jose, CA (US);
Abstract
A driver circuit, system, and method is provided. The driver circuit includes a plurality of delay cells or circuits, each comprising a set of flip-flop circuits coupled in series to produce a staged set of outputs onto an output port of the driver circuit. The staged outputs are sequentially applied to the output port at a time depending on the number of flip-flop circuits within each stage. The number of such circuits can be programmably modified so that the slew rate output of the driver circuit can be programmably changed. The driver circuit can be a low speed driver circuit clocked by a low speed clocking signal of, for example, 1.5 MHz, with the slew rate derived by a clocking signal of, for example, 480 MHz. The higher speed clocking signal clocks the flip-flop circuits, yet the output is staged so that the low speed driver circuit transitions between logic states using the higher speed clock, but at a must slower edge rate. Therefore, the driver circuit, system, and method avoids passive electrical components and the PVT fluctuations associated therewith.