The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 29, 2009

Filed:

Jul. 18, 2006
Applicants:

Toshiyuki Fukuda, Kadoma, JP;

Eizou Fujii, Kadoma, JP;

Yutaka Fukai, Kadoma, JP;

Yutaka Harada, Kadoma, JP;

Kiyokazu Itoi, Kadoma, JP;

Inventors:

Toshiyuki Fukuda, Kadoma, JP;

Eizou Fujii, Kadoma, JP;

Yutaka Fukai, Kadoma, JP;

Yutaka Harada, Kadoma, JP;

Kiyokazu Itoi, Kadoma, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/14 (2006.01); H01L 31/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor device including a package () having a plurality of wall portions () and a plurality of conductor portions (), a semiconductor element such as a solid-state image pickup device () mounted in an internal space of the base, thin metal wires () electrically connecting the semiconductor element and the conductor portions () between the wall portions (), a resin sealing material () implanted in the spaces between the wall portions (), and a closing member such as a cover glass (). The region for connecting the thin metal wires () and the wall portion () region overlap each other, so that the device can be reduced in size and in height. The cover glass () can not move easily from the correct position because the wall portions () serve as supporting columns, thereby improving the yield.


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