The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 29, 2009

Filed:

Dec. 08, 2006
Applicants:

Min-gu Kang, Seoul, KR;

Ki-hong Kim, Gyeonggi-do, KR;

Jin-bum Kim, Seoul, KR;

Jung-yun Won, Gyeonggi-do, KR;

In-sun Jung, Gyeonggi-do, KR;

Inventors:

Min-Gu Kang, Seoul, KR;

Ki-Hong Kim, Gyeonggi-do, KR;

Jin-Bum Kim, Seoul, KR;

Jung-Yun Won, Gyeonggi-do, KR;

In-Sun Jung, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01);
U.S. Cl.
CPC ...
Abstract

Methods of manufacturing a field effect transistor include forming a gate pattern on a substrate. A gate spacer is formed on a sidewall of the gate pattern. A first layer is formed from a surface of the substrate and contacting the gate spacer using a first selective epitaxial growth (SEG) process at a first temperature. A second layer is formed from a surface of the first layer and contacting the gate spacer using a second SEG process at a second temperature. The second temperature is lower than the first temperature. The first and second layers define elevated source/drain regions.


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