The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 22, 2009
Filed:
Nov. 07, 2005
Peter Chia, Hsin Tien, TW;
Chad Tsai, Hsin Tien, TW;
Jiin Lai, Hsin Tien, TW;
Edward Su, Hsin Tien, TW;
Chih-kuo Kao, Hsin Tien, TW;
Peter Chia, Hsin Tien, TW;
Chad Tsai, Hsin Tien, TW;
Jiin Lai, Hsin Tien, TW;
Edward Su, Hsin Tien, TW;
Chih-Kuo Kao, Hsin Tien, TW;
Via Technologies, Inc., Taipei Hsien, TW;
Abstract
The present computing system using PCI-E architecture includes at least one first PCI-E port, a first port-arbiter, a first URD logic, a microprocessor, a DARD logic and a device arbiter. The first port-arbiter receives a data from the first PCI-E port. The first URD logic is coupled to said first port-arbiter. The first URD logic includes an onboard range table and a PCI-E device range table for detecting the data of onboard access or peer-to-peer access. The microprocessor receives and processes the data from the first URD logic for said onboard access. The DARD logic receives the data from the microprocessor. The DARD logic decodes a device range of a downstream request of the data. The device arbiter is coupled to the DARD logic and the first URD logic for dispatching the data to one of the first PCI-E port.