The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 22, 2009
Filed:
Nov. 01, 2005
Michael G. Khazhinsky, Austin, TX (US);
Martin J. Bayer, Gilbert, AZ (US);
James W. Miller, Austin, TX (US);
Bryan D. Preble, Gilbert, AZ (US);
Michael G. Khazhinsky, Austin, TX (US);
Martin J. Bayer, Gilbert, AZ (US);
James W. Miller, Austin, TX (US);
Bryan D. Preble, Gilbert, AZ (US);
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
An integrated circuit () includes first and second power domains and a bank of input/output (I/O) cells () coupled to the first and second power domains. The bank of I/O cells () includes a first plurality of active clamps () for the first power domain and a second plurality of active clamps () for the second power domain wherein the first () and second () pluralities of active clamps overlap along the bank of I/O cells. According to one aspect each of the plurality of input/output cells () has a bonding pad () for receiving an output signal referenced to a respective first power domain, and at least one ESD protection element () for a respective second power domain. According to another aspect, each of the plurality of input/output cells () has a bonding pad () for receiving a respective output signal and at least one ESD protection element for each of a first power domain and a second power domain.