The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 22, 2009
Filed:
Sep. 18, 2003
Lifeng Wang, Beijing, CN;
KE Deng, Beijing, CN;
Baining Guo, Beijing, CN;
Joshua William Buckman, Redmond, WA (US);
Lifeng Wang, Beijing, CN;
Ke Deng, Beijing, CN;
Baining Guo, Beijing, CN;
Joshua William Buckman, Redmond, WA (US);
Microsoft Corporation, Redmond, WA (US);
Abstract
A software-implemented transform and lighting module and pipeline designed and optimized for embedded platforms (such as mobile computing devices). The transform and lighting module and pipeline includes a number of features that make it well-suited for use on embedded devices. These features include a single streamline branched architecture that allows efficient processing on a CPU of an embedded device and saves computational time. This architecture is facilitated by use of a vertex cache that stores vertices as needed to avoid duplication in processing of the vertices. A culling feature culls vertices before lighting instead of lighting all vertices. A back face culling technique examines each of the vertices to determines whether a back face of a triangle is formed. If so, then the vertex is culled. A second technique involved determining whether a vertex is outside of one view frustum clip plane. If so, then the vertex is culled.