The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 22, 2009

Filed:

Sep. 17, 2007
Applicants:

Hyeon Min Bae, Champaign, IL (US);

Naresh Ramnath Shanbhag, Champaign, IL (US);

Jonathan B. Ashbrook, Homer, IL (US);

Inventors:

Hyeon Min Bae, Champaign, IL (US);

Naresh Ramnath Shanbhag, Champaign, IL (US);

Jonathan B. Ashbrook, Homer, IL (US);

Assignee:

Finisar Corporation, Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03F 3/45 (2006.01);
U.S. Cl.
CPC ...
Abstract

An electronic amplifier circuit that provides improved gain control linearity characteristics resulting from having a controllable field effect transistor (FET) acting as a degeneration resistance (degeneration resistance FET) and a controllable load resistance FET. The overall gain function of the amplifier exhibits improved linearity in part due to the presence of the load FET, which tends to cancel the nonlinear behavior emanating from the degeneration FET. The circuit also includes a control circuit for generating non-linear control signals that are responsive to process characteristics of the FETs, such that the degeneration resistance FET and load resistance FETs may be controlled more consistently and independently from process variations.


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