The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 22, 2009
Filed:
Jul. 19, 2006
Sungkwon Lee, Eden Prairie, MN (US);
Helmut Puchner, Santa Clara, MN (US);
Sungkwon Lee, Eden Prairie, MN (US);
Helmut Puchner, Santa Clara, MN (US);
Cypress Semiconductor Corporation, San Jose, CA (US);
Abstract
A circuit having a high voltage, drain-extended (DE) metal-oxide-semiconductor (MOS) transistor and method for fabricating the same are provided. Generally, the circuit includes an n-channel (NMOS) transistor having: (i) a source and drain formed in a substrate, the source separated from the drain by a channel; and (ii) a diffused deep n-well (DNW) formed by a long, high temperature drive-in step. The DNW forms a drain-extension region for the NMOS transistor surrounding the drain and extending a predetermined distance into the channel. The drain extension region has a doping concentration lower than the source and drain to deplete during reverse biasing of the transistor, thereby raising a breakdown voltage of the transistor. Preferably, the circuit further includes a DE p-channel MOS (PMOS) transistor in which the DNW forms a well tub for the PMOS transistor, and a p-well in DNW forms a DE region therefore. Other embodiments are also disclosed.