The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 15, 2009
Filed:
Dec. 19, 2006
Michael George Ingoldby, Boulder, CO (US);
James E. Ogden, San Jose, CA (US);
Jeffrey C. Ward, Thornton, CO (US);
Stacey Secatch, Longmont, CO (US);
Restu I. Ismail, San Francisco, CA (US);
Thomas E. Fischaber, Golden, CO (US);
Michael George Ingoldby, Boulder, CO (US);
James E. Ogden, San Jose, CA (US);
Jeffrey C. Ward, Thornton, CO (US);
Stacey Secatch, Longmont, CO (US);
Restu I. Ismail, San Francisco, CA (US);
Thomas E. Fischaber, Golden, CO (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
Methods of generating a PLD design implementation according to a design architecture tailored to specified requirements. A hardware description language (HDL) description for the PLD design includes at least one parameter value for the PLD design that will affect the preferred implementation of the design. This parameter value is passed to a high-level language (HLL) function, which is used to determine a tailored design architecture in accordance with the specified needs of the target application. The HLL function returns data specifying the tailored design architecture. This data is used in generating an implementation of the PLD design that follows the constraints imposed by the tailored design architecture. The result can be, for example, a logic gate representation of the PLD design, a netlist of the design, or a bitstream implementing the design in a target PLD.