The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7590957 B1

PDF
Full Text
Expired
Date of Patent:
Sep. 15, 2009

Filed:

Aug. 24, 2006
Applicants:

Frank A. Walian, Damascus, MD (US);

John S-h Kim, Columbia, MD (US);

Inventors:

Frank A. Walian, Damascus, MD (US);

John S-H Kim, Columbia, MD (US);

Assignee:

LSI Corporation, Milpitas, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

The disclosure is directed to a method and apparatus for fixing hold violations in an integrated circuit design. The method and apparatus trace upstream along a path in the design corresponding to the hold violation, from an end point of the path toward a start point of the path, until an element is reached that corresponds to the start point or has a fanout exceeding a predetermined fanout limit. The method and apparatus then generate an output that defines a location in the design at which to insert a delay element, such that the delay element is connected to an input of an element downstream of the element reached during tracing.


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Walian, Frank. (2009). Method and apparatus for fixing best case hold time violations in an integrated circuit design (U.S. Patent No. 7590957). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7590957

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