The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 15, 2009

Filed:

May. 09, 2005
Applicants:

Stephen B. Johnson, Colorado Springs, CO (US);

Brad D. Besmer, Colorado Springs, CO (US);

Timothy E. Hoglund, Colorado Springs, CO (US);

Jana L. Richards, Colorado Springs, CO (US);

Inventors:

Stephen B. Johnson, Colorado Springs, CO (US);

Brad D. Besmer, Colorado Springs, CO (US);

Timothy E. Hoglund, Colorado Springs, CO (US);

Jana L. Richards, Colorado Springs, CO (US);

Assignee:

LSI Logic Corporation, Milpitas, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 9/26 (2006.01); G06F 9/34 (2006.01);
U.S. Cl.
CPC ...
Abstract

A memory management unit (MMU) for a device controller that provides enhanced functionality while maintaining a small physical size or footprint, such that the die size required to manufacture the memory management unit circuitry within the device controller integrated circuit device remains small notwithstanding such enhanced functionality. This compact/tiny MMU provides virtual memory addressing and memory error detection functionality while maintaining a small physical die size. The small physical die size with enhanced functionality is obtained by improvements in translating virtual to physical addressing without use of extensive translation tables, which themselves would otherwise consume memory and associated die real estate. In addition, the MMU allows a firmware image containing code and data segments to be run-time swapped between internal shared context RAM and external memory.


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