The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 15, 2009
Filed:
Sep. 20, 2006
Suresh Natarajan Rajan, San Jose, CA (US);
Keith R. Schakel, San Jose, CA (US);
Michael John Sebastian Smith, Palo Alto, CA (US);
David T. Wang, San Jose, CA (US);
Frederick Daniel Weber, San Jose, CA (US);
Suresh Natarajan Rajan, San Jose, CA (US);
Keith R. Schakel, San Jose, CA (US);
Michael John Sebastian Smith, Palo Alto, CA (US);
David T. Wang, San Jose, CA (US);
Frederick Daniel Weber, San Jose, CA (US);
MetaRAM, Inc., San Jose, CA (US);
Abstract
A memory circuit power management system and method are provided. In use, an interface circuit is in communication with a plurality of physical memory circuits and a system. The interface circuit is operable to interface the physical memory circuits and the system for simulating at least one virtual memory circuit with a first power behavior that is different from a second power behavior of the physical memory circuits.