The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 15, 2009
Filed:
Apr. 19, 2007
Katsuya Ishikawa, Kawasaki, JP;
Tatsushi Otsuka, Kawasaki, JP;
Katsuya Ishikawa, Kawasaki, JP;
Tatsushi Otsuka, Kawasaki, JP;
Fujitsu Microelectronics Limited, Tokyo, JP;
Abstract
An integrated circuit that enables a reduction in chip size and test time. This integrated circuit comprises an internal circuit; an external memory control circuit for inputting read data from an LSI tester by the use of a read command and for outputting write data to the LSI tester by the use of a write command; a test RAM including a read data storage section for storing the read data inputted from the LSI tester at a low speed and a write data storage section for storing the write data outputted from the control circuit; a test circuit for interpreting the read command and the write command issued by the external memory control circuit, for supplying, at the time of determining that the read data must be inputted to the external memory control circuit, the read data from the test RAM to the external memory control circuit at a high speed, and for supplying, at the time of determining that the write data is outputted from the external memory control circuit, the write data outputted from the external memory control circuit to the test RAM at a high speed; and a test circuit for outputting the write data stored in the test RAM to the LSI tester at a low speed.