The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 15, 2009
Filed:
Nov. 06, 2007
Manoj B. Roge, San Jose, CA (US);
Andrew Bellis, Guildford, GB;
Philip Clarke, Leatherhead, GB;
Joseph Huang, Morgan Hill, CA (US);
Michael H. M. Chu, Fremont, CA (US);
Yan Chong, San Jose, CA (US);
Manoj B. Roge, San Jose, CA (US);
Andrew Bellis, Guildford, GB;
Philip Clarke, Leatherhead, GB;
Joseph Huang, Morgan Hill, CA (US);
Michael H. M. Chu, Fremont, CA (US);
Yan Chong, San Jose, CA (US);
Altera Corporation, San Jose, CA (US);
Abstract
Circuits, methods, and apparatus that provide the calibration of input and output circuits for a high-speed memory interface. Timing errors caused by the fly-by routing of a clock signal provided by the memory interface are calibrated for both read and write paths. This includes adjusting read and write DQS signal timing for each DQ/DQS group, as well as inserting or bypassing registers when timing errors are more than one clock cycle. Timing skew caused by trace and driver mismatches between CK, DQ, and DQS signals are compensated for. One or more of these calibrations may be updated by a tracking routine during device operation.