The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 15, 2009

Filed:

Oct. 26, 2007
Applicants:

Johnson Tan, Mountain View, CA (US);

Andrew Bellis, Guildford, GB;

Philip Clarke, Leatherhead, GB;

Yan Chong, San Jose, CA (US);

Joseph Huang, Morgan Hill, CA (US);

Michael H. M. Chu, Fremont, CA (US);

Chiakang Sung, Milpitas, CA (US);

Inventors:

Johnson Tan, Mountain View, CA (US);

Andrew Bellis, Guildford, GB;

Philip Clarke, Leatherhead, GB;

Yan Chong, San Jose, CA (US);

Joseph Huang, Morgan Hill, CA (US);

Michael H. M. Chu, Fremont, CA (US);

Chiakang Sung, Milpitas, CA (US);

Assignee:

Altera Corporation, San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 7/38 (2006.01);
U.S. Cl.
CPC ...
Abstract

Circuits, methods, and apparatus for the dynamic control of calibration data that adjusts the timing of input and output signals on an integrated circuit. This dynamic control allows input and output circuits to self-calibrate by compensating for temperature and voltage changes in an efficient manner, without the need for device reconfiguration. Calibration settings can be maintained while new calibration settings are loaded. Skew between clock and data signals, as well as among multiple data signals, can be reduced. Dynamic control is achieved while consuming only a minimal resources including route paths.


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