The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 15, 2009

Filed:

Oct. 23, 2007
Applicants:

Mario E. Guzman, Mountain View, CA (US);

Christopher F. Lane, San Jose, CA (US);

Inventors:

Mario E. Guzman, Mountain View, CA (US);

Christopher F. Lane, San Jose, CA (US);

Assignee:

Altera Corporation, San Jose, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 19/003 (2006.01);
U.S. Cl.
CPC ...
Abstract

Integrated circuits such as programmable logic devices are provided that have circuit blocks such as memory blocks. The integrated circuits may be tested to determine whether the circuit blocks contain defects. If defective circuitry is identified, switching circuitry in the circuit blocks can be configured to switch redundant circuitry into use. Repairs may be made by loading repair data into fuses on the integrated circuit. Each circuit block may have an associated control circuit with a unique address. A master block repair controller may be used to route repair data to each control circuit over a shared bus using the unique addresses of the control circuits. Each control circuit may have register circuitry into which addresses and repair data are loaded. Testing circuitry may be used to supply test signals. Multiplexing circuitry can selectively route either the test signals or repair data to the control circuits over the shared bus.


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