The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7589361 B1

PDF
Full Text
Expired
Date of Patent:
Sep. 15, 2009

Filed:

Sep. 13, 2005
Applicant:

Atsushi Takahata, Osaka, JP;

Inventor:

Atsushi Takahata, Osaka, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/10 (2006.01);
U.S. Cl.
CPC ...
Abstract

In automatic placing and routing, a standard cellis composed of a P-channel transistor regionand an N-channel transistor region. The P-channel transistor regionhas a P-channel functional transistor forming region, and the N-channel transistor regionhas an N-channel functional transistor forming region. In a space region of the N-channel transistor regionother than the N-channel functional transistor forming region, a power source capacitor forming regionis formed at a portion of the P-channel transistor regionopposing the P-channel functional transistor forming region. In this region, a power source capacitor is formed to suppress the IR-Drop of a power source wiring line.


Find Patent Forward Citations

Takahata, Atsushi. (2009). Standard cells, lsi with the standard cells and layout design method for the standard cells (U.S. Patent No. 7589361). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7589361

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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