The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 08, 2009
Filed:
Aug. 25, 2006
Hiroshi Takita, Kawasaki, JP;
Takashi Maruyama, Kawasaki, JP;
Hiroshi Takita, Kawasaki, JP;
Takashi Maruyama, Kawasaki, JP;
Fujitsu Microelectronics Limited, Tokyo, JP;
Abstract
A layout determination method determines a layout of semiconductor devices that are to be created on a substrate by carrying out an exposure process. The layout determination method determines a number of semiconductor devices to be created on one substrate, based on exposure data of the semiconductor devices, a time limit of delivery of the semiconductor devices and a number of substrates to be used for production of the semiconductor devices, obtains coordinates of semiconductor devices arrangeable on the substrate, based on the exposure data, and determines the layout of the semiconductor devices to be created on the substrate, based on the exposure data, the number of semiconductor devices and the coordinates of the semiconductor devices.