The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 08, 2009
Filed:
Jul. 21, 2006
Lindor Eric Henrickson, San Jose, CA (US);
Edwin Simon Petrus, Piedmont, CA (US);
Lindor Eric Henrickson, San Jose, CA (US);
Edwin Simon Petrus, Piedmont, CA (US);
CiraNova, Inc., Santa Clara, CA (US);
Abstract
Exemplary systems and methods of laying out integrated circuits are disclosed. The systems include a layout application configured to place geometries in conformance with layout constraints transformed into composite cells. A composite cell defines a relationship between one or more cells, such as parameterized cells, and is independent of the physical topology of the cells. The exemplary systems are configured to use the composite cells to restrict a number of possible layout scenarios by generating a first layout scenario in conformance with the composite cell implementations, and to thereafter generate a second layout scenario in conformance with the constraints on all cells within the first layout scenario. Embodiments of the present invention are particularly suited to the layout of analog and mixed signal integrated circuits resulting in faster, more flexible, and more efficient layout as compared with conventional techniques which require the layout application to search through a much broader set of possible scenarios.