Clock gating in a structured asic

Abstract

Circuits and methods use clock gating to reduce power consumption in select parts of a structured ASIC. A clock distribution network includes a deterministic portion, a configurable portion, and one or more clock gating circuits. The deterministic portion employs a predetermined arrangement of conductor segments and buffers for distributing a clock signal and a clock enable signal to a plurality of predetermined locations on the device. A clock gating circuit, connected with the deterministic portion, may be placed at any of the predetermined locations, or at any location within predetermined areas associated with the predetermined locations. The clock gating circuit produces a gated clock signal output. A configurable portion and/or subportion distributes the gated clock signal output to logic elements. Depending on the value of the clock enable signal, operation of the logic elements may be suspended.