The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 08, 2009
Filed:
Jun. 29, 2005
Jerry W. Yancey, Greenville, TX (US);
Yea Z. Kuo, Rockwall, TX (US);
Jerry W. Yancey, Greenville, TX (US);
Yea Z. Kuo, Rockwall, TX (US);
L-3 Communications Integrated Systems L.P., Greenville, TX (US);
Abstract
Systems and methods for providing a weighted overlap and add (WOLA) architecture and/or for providing polyphase WOLA FFT processing that may be employed, for example, for separation or channelization of closely-spaced frequencies of an input signal. A WOLA architecture that may be implemented as first-in-first-out (FIFO) cores in an FPGA or ASIC device. The FIFO cores may be pre-existing (e.g., provided as free FIFO cores in a commercial off the shelf (COTS) FPGA device) or may be custom-programmed into a custom ASIC device.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile