The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 08, 2009

Filed:

Jun. 30, 2008
Applicants:

Seok Pyo Song, Seongnam-si, KR;

Dong Sun Sheen, Yongin-si, KR;

Young Jin Lee, Yongin-si, KR;

MI RI Lee, Icheon-si, KR;

Chi Ho Kim, Jeonju-si, KR;

Gil Jae Park, Busan, KR;

BO Min Seo, Yongin-si, KR;

Inventors:

Seok Pyo Song, Seongnam-si, KR;

Dong Sun Sheen, Yongin-si, KR;

Young Jin Lee, Yongin-si, KR;

Mi Ri Lee, Icheon-si, KR;

Chi Ho Kim, Jeonju-si, KR;

Gil Jae Park, Busan, KR;

Bo Min Seo, Yongin-si, KR;

Assignee:

Hynix Semiconductor Inc., Icheon-Si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8247 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of fabricating a non-volatile memory device includes forming a tunneling layer and a conductive layer on a semiconductor substrate, and patterning the conductive layer, the tunneling layer, and the semiconductor substrate to form a conductive pattern, a tunneling pattern, and a trench in the semiconductor substrate. The method also includes filling the trench with a insulating material, and exposing a partial sidewall of the conductive pattern. The method further includes recessing the exposed partial sidewall of the conductive pattern in an inward direction to form a floating gate. The floating gate includes a base portion and a protruding portion having a width smaller than that of the base portion. The method also includes etching the insulating layer to form an isolation layer that exposes the base portion of the floating gate. Still further, the method includes forming a dielectric layer, that extends along the base and protruding portions of the floating gate, and a control gate that covers the base and protruding portions of the floating gate.


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