The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 01, 2009
Filed:
Jun. 07, 2007
Geoffrey S. Gongwer, Los Altos, CA (US);
Daniel C. Guterman, Fremont, CA (US);
Yupin Kawing Fong, Fremont, CA (US);
Geoffrey S. Gongwer, Los Altos, CA (US);
Daniel C. Guterman, Fremont, CA (US);
Yupin Kawing Fong, Fremont, CA (US);
SanDisk Corporation, Milpitas, CA (US);
Abstract
A 'smart verify' technique, whereby multi-state memories are programmed using a verify-results-based dynamic adjustment of the multi-states verify range for sequential-state-based verify implementations, is presented. This technique can increase multi-state write speed while maintaining reliable operation within sequentially verified, multi-state memory implementations by providing 'intelligent' means to minimize the number of sequential verify operations for each program/verify/lockout step of the write sequence. At the beginning of a program/verify cycle sequence only the lowest state or states are checked during the verify phase. As lower states are reached, additional higher states are added to the verify sequence and lower states can be removed.