Method and apparatus for enabling and disabling a test mode of operation of an electronic memory device without additional interconnects or commands

Abstract

A method and apparatus allows an electronic device to operate, first, in a test mode and, second, in a functional mode, the functional mode being the normal operating mode of the device. In the test mode, input stimulus is processed by test circuitry to control device outputs according to a relatively simple algorithm suitable for test purposes. When the device is in test mode, the functional circuitry reacts to the input stimulus in the same manner it would when the device is in functional mode. However, when the device is in test mode the functional circuitry does not control the device outputs. During this time the functional circuitry is in an undefined state, as would be expected immediately after power application. When predefined input stimulus is applied to the device which could cause part of the functional circuitry to switch to a defined state, test mode is deactivated and functional mode activated. When so activated the functional circuitry, in addition to continuing to react to input stimulus as before, controls the device outputs. The two modes are successively achieved without requiring special external connections or special control commands. The test circuitry of the device is, therefore, essentially transparent unless specifically utilized, allowing the device to be used in systems which are not designed to utilize the test feature of the device as well as in those systems which do.