The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 01, 2009

Filed:

Dec. 14, 2007
Applicants:

Pete Cumming, Wickwar, GB;

Jon Mangnall, Clapton-in-Gordano, GB;

Graham Cunningham, Redland, GB;

Inventors:

Pete Cumming, Wickwar, GB;

Jon Mangnall, Clapton-in-Gordano, GB;

Graham Cunningham, Redland, GB;

Assignee:

Icera, Inc., Wilmington, MA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 19/00 (2006.01); H03K 19/096 (2006.01);
U.S. Cl.
CPC ...
Abstract

A circuit comprising: clock circuitry for supplying a first faster clock signal to a first circuit portion and a second slower clock signal to a second circuit portion, and varying the relative frequency of the first and second clock signals. Synchronisation logic generates pulses which indicate when to transfer data between the first and second circuit portions. The clock circuitry generates a first control signal at a predetermined time in each cycle of the first clock signal prior to a predetermined edge, and a second control signal at a predetermined time in each cycle of the second clock signal prior to a predetermined edge. A change in the relative frequency is conditional on a coincidence of the first and second control signals. The synchronisation generates the pulses such that there is at least one cycle of the first clock signal between those pulses, and such that there is only one of those pulses per cycle of the second clock signal.


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