Methods and computer program products for debugging clock-related scan testing failures of integrated circuits

Abstract

The present invention is directed to a method for debugging scan testing failures of integrated circuits. The method includes identifying good and bad scan paths among a set of scan paths. A scan path is bad if it is not producing any output. A scan path is good if it is producing a correct output. A clock set is generated for each scan path. The clock set includes all clock elements whose outputs impact the scan path. A union of the scan path clock sets for the bad scan paths is created. Good clock elements are removed from the union. A clock element is presumed to be good if it is associated with a good scan path. Clock elements remaining within the union of clock sets for the bad scan paths are analyzed to determine the source of errors. In one embodiment, multiple input clock elements in all bad scan paths are analyzed first, followed by analysis of single input clock elements in all bad scan paths and followed by analysis of any other clock elements in any of the bad scan paths. In an alternative embodiment, failure probabilities are associated with clock elements to prioritize analysis and debugging.