The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 25, 2009
Filed:
May. 09, 2005
Applicants:
V. V. Shyam Prasad, Bangalore, IN;
Ganapathi Hegde, Bangalore, IN;
Inventors:
V. V. Shyam Prasad, Bangalore, IN;
Ganapathi Hegde, Bangalore, IN;
Assignee:
National Semiconductor Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/12 (2006.01); G06F 13/42 (2006.01); H04L 5/00 (2006.01); H04L 7/00 (2006.01);
U.S. Cl.
CPC ...
Abstract
A method for balancing clock trees in a multi-voltage synchronous digital environment is provided that includes generating a first source clock signal in a first voltage domain based on a first mirrored clock signal in a second voltage domain. Similarly, a second source clock signal is generated in the second voltage domain based on a second mirrored clock signal in the first voltage domain.
Prasad, V. V. Shyam. (2009). Method and system for balancing clock trees in a multi-voltage synchronous digital environment (U.S. Patent No. 7581131). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7581131
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile